?catalyst semiconductor, inc., patent pending characteristics subject to change without notice doc. no. md-1082, rev. p 1 cat22c10 256-bit nonvolatile cmos static ram features single 5v supply fast ram access times: ?00ns ?00ns infinite eeprom to ram recall cmos and ttl compatible i/o power up/down protection 100,000 program/erase cycles (e 2 prom) low cmos power consumption: ?ctive: 40ma max. ?tandby: 30 a max. jedec standard pinouts: ?8-lead dip ?6-lead soic 10 year data retention commercial, industrial and automotive temperature ranges description the cat22c10 nvram is a 256-bit nonvolatile memory organized as 64 words x 4 bits. the high speed static ram array is bit for bit backed up by a nonvolatile eeprom array which allows for easy transfer of data from ram array to eeprom (store) and from eeprom to ram (recall). store operations are completed in 10ms max. and recall operations typi- cally within 1.5 s. the cat22c10 features unlimited ram write operations either through external ram pin configuration pin functions pin name function a 0 ? 5 address i/o 0 ?/o 3 data in/out we write enable cs chip select recall recall store store v cc +5v v ss ground nc no connect writes or internal recalls from eeprom. internal false store protection circuitry prohibits store operations when v cc is less than 3.0v. the cat22c10 is manufactured using catalyst? ad- vanced cmos floating gate technology. it is designed to endure 100,000 program/erase cycles (eeprom) and has a data retention of 10 years. the device is available in jedec approved 18-lead plastic dip and 16-lead soic packages. soic package (w) dip package (l) nc a 4 a 3 a 2 v ss a 1 cs store a 0 nc v cc a 5 i/o 3 i/o 2 i/o 1 i/o 0 we recall 1 2 3 4 5 6 7 8 9 14 13 11 10 12 15 16 17 18 h a l o g e n f r e e tm l e a d f r e e 1 2 3 4 5 6 7 8 14 13 11 10 9 12 15 16 a 1 a 2 a 3 a 4 a 0 a 5 v cc i/o 4 i/o 3 i/o 2 i/o 1 v ss we cs store recal l
cat22c10 2 doc. no. md-1082, rev. p mode selection (1)(2)(3) input mode cs cs cs cs cs we we we we we recall recall recall recall recall store store store store store i/o standby h x h h output high-z ram read l h h h output data ram write l l h h input data (eeprom ram) x h l h output high-z recall (eeprom ram) h x l h output high-z recall (ram eeprom) x h h l output high-z store (ram eeprom) h x h l output high-z store block diagram power-up timing (4) symbol parameter min. max. units vccsr v cc slew rate 0.5 0.005 v/ms note: (1) recall signal has priority over store signal when both are applied at the same time. (2) store is inhibited when recall is active. (3) the store operation is inhibited when v cc is below 3.0v. (4) this parameter is tested initially and after a design or process change that affects the parameter. row select column select control logic read/write circuits recall eeprom array store a 0 a 1 a 2 a 3 a 4 a 5 store recall cs we i/o 0 i/o 1 i/o 2 i/o 3 static ram array
cat22c10 3 doc. no. md-1082, rev. p absolute maximum ratings* temperature under bias ................. 55 c to +125 c storage temperature ....................... 65 c to +150 c voltage on any pin with respect to ground (2) .............. -2.0 to +vcc +2.0v v cc with respect to ground ................ -2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (3) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. reliability characteristics symbol parameter min. max. units reference test method n end (1) endurance 100,000 cycles/byte mil-std-883, test method 1033 t dr (1) data retention 10 years mil-std-883, test method 1008 v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(4) latch-up 100 ma jedec standard 17 d.c. operating characteristics v cc = +5v 10%, unless otherwise specified. limits symbol parameter min. typ. max. unit conditions i cc current consumption 40 ma all inputs = 5.5v (operating) t a = 0 c all i/o s open i sb current consumption 30 a cs = v cc (standby) all i/o s open i li input current 10 a0 v in 5.5v i lo output leakage current 10 a0 v out 5.5v v ih high level input voltage 2 v cc v v il low level input voltage 0 0.8 v v oh high level output voltage 2.4 v i oh = 2ma v ol low level output voltage 0.4 v i ol = 4.2ma v dh ram data holding voltage 1.5 5.5 v v cc capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol parameter max. unit conditions c i/o (1) input/output capacitance 10 pf v i/o = 0v c in (1) input capacitance 6 pf v in = 0v note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) the minimum dc input voltage is -0.5v. during transitions, inputs may undershoot to -2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (3) output shorted for no more than one second. no more than one output shorted at a time. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from -1v to v cc +1v.
cat22c10 4 doc. no. md-1082, rev. p a.c. characteristics, read cycle v cc = +5v 10%, unless otherwise specified. 22c10-20 22c10-30 symbol parameter min. max. min. max. unit conditions t rc read cycle time 200 300 ns c l = 100pf t aa address access time 200 300 ns +1ttl gate t co cs access time 200 300 ns v oh = 2.2v t oh output data hold time 0 0 ns v ol = 0.65v t lz (1) cs enable time 0 0 ns v ih = 2.2v t hz (1) cs disable time 100 100 ns v il = 0.65v a.c. characteristics, write cycle v cc = +5v 10%, unless otherwise specified. 22c10-20 22c10-30 symbol parameter min. max. min. max. unit conditions t wc write cycle time 200 300 ns t cw cs write pulse width 150 150 ns t as address setup time 50 50 ns c l = 100pf t wp write pulse width 150 150 ns +1ttl gate t wr write recovery time 25 25 ns v oh = 2.2v t dw data valid time 100 100 ns v ol = 0.65v t dh data hold time 0 0 ns v ih = 2.2v t wz (1) output disable time 100 100 ns v il = 0.65v t ow output enable time 0 0 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
cat22c10 5 doc. no. md-1082, rev. p a.c. characteristics, store cycle v cc = +5v 10%, unless otherwise specified. limits symbol parameter min. max. units conditions t stc store time 10 ms t stp store pulse width 200 ns c l = 100pf + 1ttl gate t stz (1) store disable time 100 ns v oh = 2.2v, v ol = 0.65v t ost (1) store enable time 0 ns v ih = 2.2v, v il = 0.65v a.c. characteristics, recall cycle v cc = +5v 10%, unless otherwise specified. limits symbol parameter min. max. units conditions t rcc recall cycle time 1.4 s t rcp recall pulse width 300 ns c l = 100pf + 1ttl gate t rcz recall disable time 100 ns v oh = 2.2v, v ol = 0.65v t orc recall enable time 0 ns v ih = 2.2v, v il = 0.65v t arc recall data access time 1.1 s note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
cat22c10 6 doc. no. md-1082, rev. p device operation the configuration of the cat22c10 allows a common address bus to be directly connected to the address inputs. additionally, the input/output (i/o) pins can be directly connected to a common i/o bus if the bus has less than 1 ttl load and 100pf capacitance. if not, the i/o path should be buffered. when the chip select ( cs ) pin goes low, the device is activated. when cs is forced high, the device goes into the standby mode and consumes very little current. with the nonvolatile functions inhibited, the device operates like a static ram. the write enable ( we ) pin selects a write operation when we is low and a read operation when we is high. in either of these modes, an array byte (4 bits) can be addressed uniquely by using the address lines (a 0 a 5 ), and that byte will be read or written to through the input/output pins (i/o 0 i/o 3 ). the nonvolatile functions are inhibited by holding the store input and the recall input high. when the recall input is taken low, it initiates a recall operation which transfers the contents of the entire eeprom array into the static ram. when the store input is taken low, it initiates a store operation which transfers the entire static ram array contents into the eeprom array. standby mode the chip select ( cs ) input controls all of the functions of the cat22c10. when a high level is supplied to the cs pin, the device goes into the standby mode where the outputs are put into a high impendance state and the power consumption is drastically reduced. with i sb less than 100 a in standby mode, the designer has the flexibility to use this part in battery operated systems. read when the chip is enabled ( cs = low), the nonvolatile functions are inhibited ( store = high and recall = high). with the write enable ( we ) pin held high, the data in the static ram array may be accessed by selecting an address with input pins a 0 a 5 . this will occur when the outputs are connected to a bus which is loaded by no more than 100pf and 1 ttl gate. if the loading is greater than this, some additional buffering circuitry is recommended. figure 1. read cycle timing address cs data i/o t rc t co t aa t lz t oh t hz high-z data valid
cat22c10 7 doc. no. md-1082, rev. p write with the chip enabled and the nonvolatile functions inhibited, the write enable ( we ) pin will select the write mode when driven to a low level. in this mode, the address must be supplied for the byte being written. after the set-up time (t as ), the input data must be supplied to pins i/o 0 i/o 3 . when these conditions, in- figure 2. write cycle timing figure 3. early write cycle timing cluding the write pulse width time (t wp ) are met, the data will be written to the specified location in the static ram. a write function may also be initiated from the standby mode by driving we low, inhibiting the nonvolatile func- tions, supplying valid addresses, and then taking cs low and supplying input data. t wc t as t wr data valid cs data in address we t wp t dw t cw t dh data out high-z t wc t as t wr data valid cs data in address we t wp t dw t cw t dh data out t wz t ow high-z
cat22c10 8 doc. no. md-1082, rev. p recall at anytime, except during a store operation, taking the recall pin low will initiate a recall operation. this is independent of the state of cs , we , or a 0 a 5 . after the recall pin has been held low for the duration of the recall pulse width (t rcp ), the recall will continue inde- pendent of any other inputs. during the recall, the entire contents of the eeprom array is transferred to the static ram array. the first byte of data may be externally accessed after the recalled data access time from end of recall (t arc ) is met. after this, any other byte may be accessed by using the normal read mode. if the recall pin is held low for the entire recall cycle time (t rcc ), the contents of the static ram may be immediately accessed by using the normal read mode. a recall operation can be performed an unlimited num- ber of times without affecting the integrity of the data. the outputs i/o 0 i/o 3 will go into the high impedance state as long as the recall signal is held low. store at any time, except during a recall operation, taking the store pin low will initiate a store operation. this takes place independent of the state of cs , we or a 0 a 5 . the store pin must be held low for the duration of the store pulse width (t stp ) to ensure that a store operation is initiated. once initiated, the store pin becomes a don t care , and the store operation will complete its transfer of the entire contents of the static ram array into the eeprom array within the store cycle time (t stc ). if a store operation is initiated during a write cycle, the contents of the addressed static ram byte and its corresponding byte in the eeprom array will be un- known. during the store operation, the outputs are in a high impedance state. a minimum of 100,000 store opera- tions can be performed reliably and the data written into the eeprom array has a minimum data retention time of 10 years. data protection during power-up and power-down the cat22c10 has on-chip circuitry which will prevent a store operation from occurring when v cc falls below 3.0v typ. this function eliminates the potential hazard of spurious signals initiating a store operation when the system power is below 3.0v typ. figure 4. recall cycle timing figure 5. store cycle timing cs data i/o recall address data undefined data valid high-z t rcz t orc t arc t rcp t rcc store data i/o t stz high-z t stp t stc
cat22c10 9 doc. no. md-1082, rev. p example of ordering information prefix device # suffix 22c10 w i t1 product number 22c10 20 cat company id t: tape & reel 1: 1,000/reel package l: pdip w: soic, jedec speed 20: 200ns 30: 300ns temperature range i = industrial (-40 c to +85 c) e = extended (-40 c to +125 c) (4) notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the device used in the above example is a cat22c10wi-20t1 (soic, industrial temperature, 200ns, tape & reel, 1,000/reel). (3) for additional package option please contact your nearest catalyst semiconductor sales office. (4) extended temperature available upon request.
publication #: md-1082 revison: p issue date: 06/24/08 catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com copyrights, trademarks and patents ?catalyst semiconductor, inc. trademarks and registered trademarks of catalyst semiconductor include each of the following: adaptive analog , beyond memory , dpp , ezdim , ldd , minipot , quad-mode and quantum charge programmable catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history e t a dn o i s i v e rn o i t p i r c s e d 4 0 - r p a - 6 1o o g o l e e r f d a e l d d a s e r u t a e f e t a d p u n o i t a r u g i f n o c n i p e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u r e b m u n n o i s i v e r e t a d p u 8 0 - n u j - 4 2p n o i t a m r o f n i g n i r e d r o f o e l p m a x e e t a d p u
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